1. Field of the Invention
The invention generally relates to a package structure and a manufacturing process, and more particularly, to a multi-chip package structure, a wafer level chip package structure and a manufacturing process thereof.
2. Description of Related Art
The integrated circuit chips (IC chips) are required to more offer powerful functions as electronic products develop toward high functionality, high-speed signal transmission and high density of circuit elements. Moreover, more passive devices are demanded for consumer electronic products. However, under the developing trends of electronic products for miniaturization, lightweight, and low cost, the IC packaging industry is concerned about how to accommodate numerous electronic components or devices in the limited packaging space. In order to meet the above requests, packaging technology gradually moves towards a system integration phase of system in package (SIP), and more particularly to the packaging of multi-chip module (MCM).
Using a multi-chip package structure an example, it is mainly to dispose a first chip on a second chip by a face-to-face method, and then to use a conductive bump as an electrically connection media between the chips, wherein the second chip will be electrically connected with a circuit board by means of using a bump or wire bonding.
In such package structure, since the space on the chips increasingly narrows, when a size of the first chip is close to that of the second chip, an edge of the first chip will be very close to the conductive bump, which is configured to connect to the circuit board, on the second chip. Therefore, when filling an underfill in-between the first chip and the second chip, the underfill can easily overflow to a solder pad of the conductive bump, which is configured to connect to the circuit board, on the second chip, and thereby influence the electrical connection reliability between the second chip and the circuit board.